Where AI Meets Open Inference

2026 marks a pivotal inflection point as RISC-V evolves from an open-standard architecture into a mainstream platform for AI inference. With the ratification of the RVA23 standard and the maturation of Vector Extensions (RVV 1.0), RISC-V has moved beyond early adoption, demonstrating strong competitiveness across Edge AI, industrial automation, smart cockpit systems, and customized inference servers.

The 2026 RISC-V Taipei Day forum will spotlight key technical milestones and the structural evolution of the ecosystem, examining how RISC-V leverages deep customization and superior performance-per-watt to outperform traditional architectures in Transformer workloads. Industry leaders—including Andes Technology, DeepComputing, Semidynamics, StarFive, RISC-V International, and the RISE (RISC-V Software Ecosystem) Project—will join together and share the latest advancements spanning AI inference chips to the global software ecosystem. 

In addition to the full-day RISC-V Taipei Day forum, the RISC-V Taiwan Alliance will host a four-day RISC-V Pavilion during COMPUTEX 2026, showcasing end-to-end technical solutions. Through this integrated program of high-level forum and curated technology showcases, the initiative will explore the convergence of AI and open-standard inference, driving industry innovation and expanding global ecosystem collaboration.

We cordially invite you to witness the golden era of open architectures, where RISC-V’s unparalleled flexibility enables algorithm-level innovation to translate directly into hardware optimization, redefining the economics of AI computing.

 

RISC-V Pavilion @ COMPUTEX

Time: June 02-05
Location: M1111a, 4F, Nangang Exhibition Hall 1

RISC-V Conference

Time: 10:00-17:00, June 3
Location: Room 505bc, 5F, Nangang Exhibition Hall 1

 

Agenda

Welcome and Registration

Welcome Keynote:
RISC-V Now for Taiwan and the World

Frankwell Lin|Chairman, RISC-V Taiwan Alliance | Chairman and CEO, Andes Technology

Taiwan is in the center of semiconductor, chip, IT, system design and manufacturing industries. From TSMC, Mediatek to Asus to Foxconn, In this presentation, RISC-V International (RVI) effort and achievement will be reviewed, RISC-V is mature and strong for semiconductor electronic microsystem, which mostly are made in the form of chips,. Since chip manufacturing is the strength of Taiwan, so RISC-V already started to contribute to Taiwan industry and society. AI becomes so important, the way of using RISC-V to design AI application system will be suggested. Especially for edge AI, inferencing devices shall be the strength to Taiwan’s chip design and ICT industry in near future. Action taken to speed up audiences’ organization in adapting RISC-V based solution is suggested. General purpose application processing leveraging RISC-V are trend of applications for ADAS, robot, humanroid, automotive application, handheld platform and wearable devices, the skill to do these will also be covered in this speech. As a summary, RISC-V for now, its strength, superiority, and mass production proof have proven its maturity that may help Taiwan and the World to move faster, more reliable, and more successful.

Welcome Remark

Dr. Alex Wang | Chairman, Internet of Intelligent Agent Association (IIAA)

TBC.

Welcome Remark

TBC.  TBC.

Group Photo

TBC.

Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.

TBC.
 

Innovating Next-Generation SoC with the Latest Andes RISC-V Solutions Now!  

Dr. Charlie Su | President and CTO, Andes Technology

TBC.

The RVA23 Laptop Era Begins with DC-ROMA RISC-V Mainboard III

Yuning Liang | Founder & CEO, DeepComputing

As RISC-V gains momentum across the computing industry, the emergence of standardized profiles such as RVA23 marks a major step toward mainstream adoption. The DC-ROMA RISC-V Mainboard III demonstrates how these advancements are enabling practical RISC-V personal computers.

This session introduces the DC-ROMA Mainboard III for Framework Laptop 13, powered by the SpacemiT K3 AI SoC with RVA23 support. We will highlight how the platform combines modular hardware, AI computing capability, and open-source software to create a powerful development environment for RISC-V.

Attendees will learn how the platform supports developers exploring AI, operating systems, and application development on RISC-V, and how standardized profiles like RVA23 are accelerating the transition of RISC-V from embedded systems to mainstream computing.

Scaling AI Workloads with Semidynamics RISC-V Cores

Miquel Izquierdo | VP of Engineering, Semidynamics

As VP of Hardware, Miquel Izquierdo is instrumental in leading the end-to-end development life cycle of Semidynamics’ AI systems. From initial architecture to final rack testing, he provides the strategic direction necessary to integrate silicon design, verification, and advanced packaging into a cohesive hardware platform. Miquel serves as a key driver of PPA (Power, Performance, and Area) optimization, ensuring the company’s systems set new industry benchmarks for commercial excellence and global scalability.

Miquel brings deep expertise in performance optimization and system architecture, with a career defined by extracting maximum efficiency from high-density compute environments. He is a specialist in advanced networking, having architected mission-critical interconnect fabrics both on-chip and at the rack-to-rack level. He holds degrees in Computer Engineering and Electronics, complemented by a Master’s in Electrical Engineering and Computer Science from the University of California. At Semidynamics, his mission is to deliver a transformative hardware platform that provides the massive computational capacity required for the full realization of large-scale AI.

The first RISC-V-based SoC for data center management

Jay Zhou | Vice President, StarFive

The BMC (Baseboard Management Controller) chip enables reliable, secure, and intelligent operation and management of large-scale computing clusters. StarFive Technology has officially launched the world’s first RISC-V BMC chip with world-class functionality and performance, marking the first large-scale commercial deployment of RISC-V in data centers. The chip adopts StarFive’s self-developed high energy-efficiency RISC‑V CPU IP and NoC IP, which also signifies that StarFive’s RISC‑V CPU subsystem solution has been silicon- proven.

Lucky Draw

Lunch Break and Social Networking @ RISC-V Pavilion (Booth M111a)

Welcome and Registration

Keynote: Inventing the new Era of Computing with RISC-V

Andrea Gallo | CEO, RISC-V International

The power of computing is changing the world at an ever accelerating pace, with revolutionary capabilities in AI giving us new ways of interacting with information, knowledge, and the real world around us. Each new era of computing gives huge potential for previously unimaginable new products, services and businesses, but delivering on the full promise of AI requires new architectures and capabilities, and for us to think about computing in new ways. In this talk we will outline how the RISC-V open standard underpins this new future of computing in both the virtual and the real world. We will discuss the how the design freedom enabled by RISC-V unlocks an approach to innovation not previously possible, how RISC-V enables hardware and software development as one optimized process rather than two, and also the developments in the standard that will underpin the future, across AI in the datacenter, on your personal devices, and in the physical AI, robotic and mobility applications we will rely on and start to take for granted. Come to this session to discover how RISC-V can deliver your next era of computing.

Poster Session

TBC. TBC.
 

TBC.

Panel Discussion

Moderator:
Dr. KC Liu |  Director of Taiwan Ecosystem, Edge AI Foundation
Panelist:
Frankwell Lin | Chairman, RISC-V Taiwan Alliance
Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.
Andrea Gallo | CEOs, RISC-V International

Dr. Charlie Su | President and CTO, Andes Technology
Brian "RedBeard" Harrington | Co-chair of Technical Steering Committee, Red Hat

Lucky Draw

Closing and Networking

SPEAKERS


Dr. Charlie Su
President and CTO, Andes Technology

Member of the Technical Steering Committee of RISC-V International
Member of the Governing Board of RISE project (RISC-V Software Ecosystem)

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Contact us

RISC-V TAIWAN ALLIANCE
(RVTA)
Sherry Wang

Tel

Sherry Wang
+886-2-2577-4249 ext. 246

Organizer
Co-organizer