Where AI Meets Open Inference

2026年是 RISC-V 從開放架構躍升為 AI 推論主流的關鍵元年。隨著 RVA23標準定案與向量運算擴展(RVV 1.0)成熟,RISC-V 已跨越創新門檻,在邊緣 AI與工業自動化、智慧座艙及客製化推論伺服器等多項領域展現強大競爭力。

2026 RISC-V Taipei Day論壇將聚焦RISC-V 的技術指標與生態質變,探討其如何憑藉高度客製化與優異效能功耗比,在Transformer 模型運算中超越傳統架構。現場將邀請 Andes、DeepComputing、Semidynamics、StarFive、RISC-V International及RISE軟體生態聯盟等領袖,分享從AI推論晶片到全球生態系的最新進展。

除了RISC-V Taipei Day全日精彩論壇,台灣RISC-V聯盟將同步於COMPUTEX 展期規劃為期四天的RISC-V技術方案主題展示,透過論壇與展示,共同探討 AI 與開放推論的交會點,推動產業創新並擴大全球生態系合作。誠摯邀請您見證開放架構的黃金年代,探究 RISC-V 如何以極致自由度,讓演算法創新直接轉化為硬體結構的優化,重新定義 AI 算力經濟學。

 

 

RISC-V Pavilion @ COMPUTEX

Time: June 2-5
Location: M1111a, 4F, Nangang Exhibition Hall 1

RISC-V Conference

Time: 10:00-16:30, June 3
Location: Room 505bc, 5F, Nangang Exhibition Hall 1

 

精彩議程

報到與入場

Welcome Keynote:
RISC-V Now for Taiwan and the World

林志明|台灣RISC-V聯盟 會長, 晶心科技 董事長暨執行長

Taiwan is in the center of semiconductor, chip, IT, system design and manufacturing industries. From TSMC, Mediatek to Asus to Foxconn, In this presentation, RISC-V International (RVI) effort and achievement will be reviewed, RISC-V is mature and strong for semiconductor electronic microsystem, which mostly are made in the form of chips,. Since chip manufacturing is the strength of Taiwan, so RISC-V already started to contribute to Taiwan industry and society. AI becomes so important, the way of using RISC-V to design AI application system will be suggested. Especially for edge AI, inferencing devices shall be the strength to Taiwan’s chip design and ICT industry in near future. Action taken to speed up audiences’ organization in adapting RISC-V based solution is suggested. General purpose application processing leveraging RISC-V are trend of applications for ADAS, robot, humanroid, automotive application, handheld platform and wearable devices, the skill to do these will also be covered in this speech. As a summary, RISC-V for now, its strength, superiority, and mass production proof have proven its maturity that may help Taiwan and the World to move faster, more reliable, and more successful.

Welcome Remark

待確認 | 待確認

待確認

Welcome Remark

待確認 | 待確認

Group Photo

RISC-V – An Open Standard designed for Open Innovation

Lu Dai | Board Chair, RISC-V International | VP of Technical Standards, Qualcomm Technologies, Inc.

This session presents RISC-V as a modern, open instruction set architecture standard that enables scalable, customizable, and royalty-free innovation across computing. It highlights the benefits of open standards in driving global collaboration, reducing barriers to entry, and accelerating advancements in areas such as AI, security, and system design, while outlining key ecosystem developments and ongoing technical initiatives. 
 

Innovating Next-Generation SoCs with the Latest Andes RISC-V Solutions Now!

蘇泓萌 博士 | 晶心科技 總經理暨技術長

憑藉 RISC-V 生態系統的實力,晶心科技已推動商業 RISC-V 解決方案廣泛應用於各個領域,包括 AI/ML、車用電子、5G/網路通訊、MCU/MPU、多媒體、感測器處理、儲存裝置、穿戴式裝置及無線連接。其中,從邊緣到雲端的 AI/ML 是近年來驅動創新的關鍵。 本演講提供晶心科技處理器 IP 與軟體的最新開發進展。硬體方面,將介紹增強型 AI 優化核心與亂序執行(OOO)處理器,以及即將推出的車規級與精簡型核心解決方案。軟體方面,我們將涵蓋近期進展,包括用於可信執行環境(TEE)的安全監控器、車用軟體測試庫(STL)、用於自動效能調優的 AutoOpTune™,以及其他提升系統效能與開發效率的工具。

The RVA23 Laptop Era Begins with DC-ROMA RISC-V Mainboard III

Yuning Liang | Founder & CEO, DeepComputing

As RISC-V gains momentum across the computing industry, the emergence of standardized profiles such as RVA23 marks a major step toward mainstream adoption. The DC-ROMA RISC-V Mainboard III demonstrates how these advancements are enabling practical RISC-V personal computers.

This session introduces the DC-ROMA Mainboard III for Framework Laptop 13, powered by the SpacemiT K3 AI SoC with RVA23 support. We will highlight how the platform combines modular hardware, AI computing capability, and open-source software to create a powerful development environment for RISC-V.

Attendees will learn how the platform supports developers exploring AI, operating systems, and application development on RISC-V, and how standardized profiles like RVA23 are accelerating the transition of RISC-V from embedded systems to mainstream computing.

Scaling AI Workloads with Semidynamics RISC-V Cores

Miquel Izquierdo | VP of Engineering, Semidynamics

AI's rapid growth (LLMs, generative frameworks) is stressing datacenters with huge memory, bandwidth, and power demands. Semidynamics addresses this by rethinking compute, from silicon to rack. Our core uses highly customizable RISC-V IP with advanced vector/tensor units. A key feature, Gazillion Misses, is a proprietary technology that tolerates extreme memory latency, effectively breaking the "memory wall" by ensuring processing units are constantly fed.

RISC-V's open ecosystem is a critical advantage. Using standard toolchains (GCC, LLVM) provides full compiler transparency and portability, avoiding proprietary SDK costs and vendor lock-in. This openness allows free auditing, optimization, and migration of AI software.

True AI scalability demands a tightly coupled design focused on data locality and power efficiency. Infrastructure executives will learn how Semidynamics' unified approach—harmonizing the core with a massive, memory-first rack architecture—delivers unparalleled throughput for the next generation of datacenter computing without proprietary dependency.

首个基于RISC-V的数据中心管理芯片

周杰 | 副總裁, 賽昉科技

伺服器 BMC晶片(基板管理晶片)是大規模算力集群穩定、安全、智慧化運行的保障。賽昉科技重磅推出全球第一款RISC-V BMC晶片,功能和性能達到國際一流水準,將成為RISC-V在資料中心場景第一個規模化商用的晶片產品。該晶片採用賽昉科技自研的高能效比RISC-V CPU IP和NoC IP,也標誌著賽昉科技的RISC-V CPU子系統解決方案得到量產驗證。

Lucky Draw

Lunch Break and Social Networking @ RISC-V Pavilion (Booth M1111a)

報到與入場

Keynote: Inventing the new Era of Computing with RISC-V

Andrea Gallo | CEO, RISC-V International

The power of computing is changing the world at an ever accelerating pace, with revolutionary capabilities in AI giving us new ways of interacting with information, knowledge, and the real world around us. Each new era of computing gives huge potential for previously unimaginable new products, services and businesses, but delivering on the full promise of AI requires new architectures and capabilities, and for us to think about computing in new ways. In this talk we will outline how the RISC-V open standard underpins this new future of computing in both the virtual and the real world. We will discuss the how the design freedom enabled by RISC-V unlocks an approach to innovation not previously possible, how RISC-V enables hardware and software development as one optimized process rather than two, and also the developments in the standard that will underpin the future, across AI in the datacenter, on your personal devices, and in the physical AI, robotic and mobility applications we will rely on and start to take for granted. Come to this session to discover how RISC-V can deliver your next era of computing.

Poster Session

國立陽明交通大學資訊工程學系、國立成功大學電機工程學系、國立清華大學計算機科學與技術系

1. 國立陽明交通大學資訊工程學系 | 謝翔丞 | KAIDA:基於 Kortex 的代理式 IC 設計自動化——RISC-V CPU 端到端設計、驗證與 GDS 生成
2. 國立成功大學電機工程學系 |  許翔皓 | V-MUSE:針對 RISC-V 指令集擴展之基於向量的巨集到微指令統一計分板
3. 國立清華大學計算機科學與技術系 | 蘇家輝 | 基於RISC-V P extension的正規化驗證
4. 國立陽明交通大學資訊工程學系 | 蔡承恩 | 實現RISC-V SoC向量處理器來加速邊緣AI模型推論

Panel Discussion

主持人:
劉廣治博士 |  台灣生態系總監, Edge AI Foundation
與談人:
Frankwell Lin | Chairman, RISC-V Taiwan Alliance
Lu Dai | Board Chair, RISC-V International | VP of Technical Standards, Qualcomm Technologies
Andrea Gallo | CEOs, RISC-V International
Dr. Charlie Su | President and CTO, Andes Technology
Brian "RedBeard" Harrington | Co-chair of Technical Steering Committee, Red Hat
Dr. BC Lai | Professor, Dept. of Electronics Engineering, NYCU

Lucky Draw

賦歸與交流

貴賓介紹

贊助夥伴

Platinum

Golden

Silver

Special Partner

聯絡我們

台灣RISC-V聯盟
RISC-V TAIWAN ALLIANCE(RVTA)
王小姐

Organizer
Co-organizer