2025 RISC-V Taipei Day

Agenda

09:30 - 10:00

Welcome and Registration

10:00 - 10:15

Welcome Keynote

Frankwell Lin｜Chairman, RISC-V Taiwan Alliance | Chairman and CEO, Andes Technology

Taiwan is in the center of semiconductor, chip, IT, system design and manufacturing industries. From TSMC, Mediatek to Asus to Foxconn, there are so much business opportunity. IC design, manufacturing and application is the way to realize your value in Taiwan then export to the world no matter where you are based. Now RISC-V is experiencing this fantastic journey every day, more RISC-V IP, RISC-V based chips for various applications will be presented in this speech. RISC-V International Association (RVI) has done great job in raising RISC-V open standard with its ISA and specifications and eco-systems, so numerous application specific chips can been seen in the market, we encourage you to check out RISC-V IP if you are in chip design industry, or RISC-V based chips if you are in IT, OEM/ODM, system industries. Or, you will be excited to join in RISC-V ecosystem to provide your solution to the industries in Taiwan then the world. Supply chain based on RISC-V is so mature, now you should think about how to leverage it to win your success.

10:15 - 10:20

Welcome Remark

Alex Wang | Chairman, Taiwan IoT Technology and Industry Association, TwIoTA

The automotive and data center industries are experiencing a surge in the quantity and complexity of semiconductor content. Along with traditional performance, power, and area objectives, these markets also require dependability, which includes functional safety, reliability, and availability. Therefore, semiconductors for these applications must be both reliable, reducing their likelihood of failure, and resilient, improving their ability to recover from failure. This presentation reviews some of the challenges associated with achieving these objectives and explores how automation and standardization can play a vital role in meeting these new requirements.

10:20 - 10:25

Welcome Remark

Jian-Heng Wu | Senior Technical Specialist, Administration for Digital Industries (ADI), Ministry of Digital Affairs (moda)

10:25 – 10:30

Group Photo

10:30 - 10:45

Keynote 1

Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.

From its origins at UC Berkeley, led by pioneers like Krste Asanović and David Patterson, RISC-V emerged with a radical vision: instruction sets should be free. Today, that belief has propelled RISC-V beyond academia into a global force—open, standardized, internationally recognized, royalty-free, and highly extensible.

We have built a thriving ecosystem with growing membership and a maturing, complete architecture. But where do we go from here? The possibilities are boundless—custom silicon, vertical integration, AI-driven innovation, enhanced security, and full-stack solutions that redefine computing.

To get there, we must remain customer-focused and developer-first, ensuring RISC-V continues to break barriers. Join us as we explore the future of an ISA designed not just to compete but to revolutionize. The journey has just begun.

10:45 - 11:05

Empowering Innovations in Modern Computing with RISC-V

Dr. Charlie Su | President and CTO, Andes Technology

RISC-V has rapidly gained traction across a wide range of applications, including automotive, 5G/networking, MCU/MPU, multimedia, storage, sensor processing, wearables, and wireless connectivity. Particularly prominent are emerging AI/ML applications from edge to cloud. As the RTOS, Linux, and Android ecosystems for RISC-V continue to mature, RISC-V cores are increasingly being used as main CPUs in embedded devices, personal computing and even servers. These advancements are significantly boosting RISC-V's market presence in the computing industry in the coming years.

In this talk, we will discuss four key elements in modern computing: namely AI/ML Accelerations, Embedded and Real-Time Processing, Safety and Security, and Application Processing. We will then show how the RISC-V architecture and ecosystem address them, using Andes solutions as examples.

11:05 - 11:25

Scaling Open Compute: RISC-V, Chiplets, and the Future of AI and Robotics

Luke Yen | Fellow of RISC-V CPU and Machine Learning Architectures, Tenstorrent

As artificial intelligence and autonomous systems become increasingly pervasive, the demand for scalable, high-performance, and open computing platforms is more critical than ever. This presentation outlines Tenstorrent’s approach to advancing RISC-V beyond its embedded roots into mainstream high-performance and automotive markets through mature IP and modular architecture.We introduce Tenstorrent’s RISC-V CPU roadmap, featuring the Ascalon and Callandor cores, designed for high SPECINT performance, and the Ascalon-Auto variant, which incorporates ISO 26262-compliant safety features for ADAS and autonomous driving applications. These processors are implemented using chiplet-based design and are paired with Tensix AI accelerators, enabling efficient support for AI workloads across edge devices, data centers, and automotive platforms. Central to this platform strategy is the Open Chiplet Architecture (OCA)—a layered, open standard that facilitates interoperability across chiplets from different vendors. OCA standardizes interfaces across software, system management, transport, and physical layers, enabling modular, composable system integration and fostering a collaborative ecosystem for heterogeneous compute systems.

Together, these technologies represent a unified hardware-software strategy to support ubiquitous AI computing. They position RISC-V as a competitive, open alternative to proprietary architectures, ready to power the next generation of AI-enabled and automotive systems. This presentation underscores the role of openness, scalability, and performance in shaping the future of personalized and distributed intelligence through high-performance RISC-V platforms.

11:25 - 11:45

Skymizer HyperThought : Hyper-threading Language Processing Units for Large Language Model

Luba Tang | Founder & CTO, Skymizer

Large Language Models (LLMs) are rapidly becoming integral to a wide range of computing platforms—from data centers to smartphones and even microcontrollers. As interest in deploying LLMs across diverse systems grows, so does the need for domain-specific hardware acceleration. However, designing and implementing a hyperscale Language Processing Unit (LPU) introduces significant challenges. In this talk, we will explore key issues including hardware/software co-design, verification complexity, and SoC architecture exploration.

11:45 - 11:55

Lucky Draw

11:55 - 13:30

Lunch Break

13:30 - 14:00

Welcome and Registration

14:00 - 14:15

Unleashing the Potential of RISC-V Through Open Source Collaboration

Ruinland Tsai | Chair of System Library Working Group, RISE

The RISC-V ecosystem is rapidly evolving, driven by a commitment to openness and collaboration. This talk explores the momentum of RISC-V, highlighting its potential to surpass established architectures like Arm, and emphasizes the importance of mobilizing its software ecosystem. We'll delve into key strategies for fostering this growth: enhancing collaboration and community engagement, investing in fundamental software stack components, and committing to iterative performance optimization.

This presentation will introduce the RISE project, an exciting collaboration that is driving the creation, optimization and upstreaming of open source software that can be efficiently harnessed by the RISC-V ecosystem.

This presentation will introduce the RISE project, an exciting We believe that RISC-V offers a great opportunity for companies in Asia, particularly those in Taiwan, to deliver increased value to its customers through innovation at both hardware and software levels. This presentation will discuss some specific examples where the introduction of optimized-for-purpose hardware, coupled with open-source technology unlocks the full potential of RISC-V, paving the way for a future defined by open, collaborative, and forward-thinking technology.

14:15 - 14:30

The Significance of the RVA23 Profile and Platform Specifications in Advancing RISC-V Ecosystem Development

Mark Hayter | Co-Founder and Chief Strategy Officer, Rivos Inc.

Standard ISAs are critical to the growth of both hardware and software ecosystems, promoting compatibility, innovation and adoption. They must evolve over time as seen with feature bits in x86 and Arm architecture versions. The RVA23 profile represents a key development in the RISC-V architecture, standardizing the 64-bit application processors ISA for seamless software portability across hardware implementations. This simplifies development and supports RISC-V adoption in areas like servers, automotive and client devices, where binary compatibility is important. This presentation will look at the impact RVA23 will have on high-performance applications processors and their adoption across a range of end use cases.

The RVA23 profile introduces significant features, including the Vector and Hypervisor extensions, designed to meet the needs of high-performance computing. The Vector extension enhances RISC-V’s parallel data processing, benefiting workloads like machine learning and scientific computing. The Hypervisor extension enables the virtualization of servers, supporting scalable and secure cloud infrastructure and enterprise applications.

A core advantage of the RVA23 profile is ensuring software compatibility across various hardware implementations, enabling the distribution of binary packages that work across different RISC-V vendors. This is especially useful for Linux distributions (like Ubuntu, RHEL) and Android, where apps are downloaded in binary form that works for all users. The RVA23 profile defines instructions that compilers can safely generate for all implementations.

Fully enabling a Linux distribution requires certainty in the hardware and firmware features which is provided by the Platform Specifications. The Server Platform Specification describes not only the need for the RVA23 Profile but also hardware requirements from the Server SoC Specification and firmware details from the Boot And Runtime Services Specification.

For companies developing 64-bit server processors, adopting the RVA23 profile and Server Platform Specification ensures consistent software distribution, compatibility and high performance.

14:30 - 14:45

Revolutionizing AI Computing with World's First RISC-V 50 TOPS AI PC

Yuning Liang | Founder & CEO, DeepComputing

In the rapidly evolving world of artificial intelligence, breakthroughs in large language models (LLMs) are driving an unprecedented demand for high-performance AI computing devices—prioritizing local data privacy, security, and on-device AI processing.

At CES 2025, Nvidia showcased the future of AI-powered laptops with its GeForce RTX 50 Series, pushing AI-driven graphics and processing to new heights. Yet, a new frontier is emerging—RISC-V AI computing—ushering in an open, customizable era for AI hardware.

DeepComputing is leading this shift by developing the world’s first RISC-V 50 TOPS AI PC. This revolutionary device is built in collaboration with Framework, RISC-V SoC manufacturers, open-source OS leaders Canonical and Fedora, and AI innovators utilizing DeepSeek LLM models—powering AI applications like VLC Media Player and beyond.

This session will uncover how DeepComputing’s AI PC harnesses the open-source flexibility of RISC-V, enabling vertically optimized AI ecosystems. We’ll dive into the dual-die AI SoC architecture, the 64-bit RISC-V CPU with out-of-order execution, and how the system accelerates AI workloads—delivering faster inference, seamless AI app integration, and cloud-free AI experiences. Join us to explore how RISC-V + AI is not just a technological leap but a movement—pioneering a future of modular, sustainable, and developer-empowered AI computing.

14:45 - 15:00

RISC-V accelerating the future of AI & Automotive computing

Nathan Ma | AVP of Marketing and Strategy, Nuclei System Technology

RISC-V is revolutionizing computing paradigms across AI and automotive applications, offering an unprecedented combination of architectural flexibility, scalability, customization and cost efficiency. In AI applications, RISC-V's modular design enables customized acceleration for AI innovations both for edge & cloud, while in automotive systems, its openness facilitates the trend of software defining vehicles.

As a leading RISC-V processor IP provider, Nuclei's RISC-V products have been adopted across diverse applications, from AI accelerators to automotive MCUs/SoCs. Nuclei is the world's first RISC-V IP company to achieve ISO26262 ASIL-D product certification. This achievement not only validates our technological capabilities but also demonstrates RISC-V's readiness for the most demanding safety-critical applications.

In this presentation, we will share our hands-on experience in developing and deploying RISC-V solutions for AI and automotive applications. We'll provide in-depth technical insights into:

Our RVV1.0 vector extension implementation supporting up to 1024-bit VLEN & DLEN, optimized for the offloading of specific AI layers or operators
We'll also share some successful cases in both AI acceleration and automotive computing.

15:00-15:15

Autonomy Robotic System Architecture for the Quantum Era — Building AI + PQC Secure Robotics with RISC-V Architecture

Ming-Yang Chih | Founder & CEO, Chelpis Quantum Corporation

As autonomous systems enter the age of AI-driven decision-making, quantum-era cybersecurity challenges are rising rapidly. This session will present Chelpis’s pioneering RISC-V-based SoC architecture, designed for next-generation robotics—combining real-time AI processing, sensor fusion, and post-quantum cryptography (PQC) into a modular, secure edge platform. Use cases such as industrial quadrupeds, autonomous drones, and collaborative logistics robots will be introduced. The talk will also explore how Taiwan can position itself at the forefront of secure, intelligent robotic systems and quantum-resilient chip technologies.

15:15-15:30

Enabling NPU AI Compute entirely on RISC-V ISA

Roger Espasa | Founder & CEO, Semidynamics

In recent deployments, RISC-V has been used in AI applications, primarily for controlling or supporting AI algorithms. To address NPU applications, custom hardware has traditionally been placed adjacent to the RISC-V CPU, effectively shifting the pre-RISC-V proprietary accelerator approach into the RISC-V ecosystem—bringing the same legacy restrictions into the open ISA RISC-V world.

Semidynamics' novel approach eliminates this issue by introducing a RISC-V ISA-only, performance-optimized compute engine that integrates CPU, vector, and tensor operations into a single compute element. This innovation enables RISC-V to enter the previously unaddressed NPU marketplace. With configurable performance ranging from 8 to 64 TOPS, this RISC-V engine delivers efficient AI acceleration for LLMs, deep learning, edge AI, and datacenters.

15:30 - 16:10

Panel Discussion

Moderator:
Dr. Jefferey Chiu | CEO, Ansforce Inc.
Panelists:
Frankwell Lin | Chairman, RISC-V Taiwan Alliance
Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.
Dr. Charlie Su | President and CTO, Andes Technology
Luke Yen | Fellow of RISC-V CPU and Machine Learning Architectures, Tenstorrent
William Wei | CMO and EVP, Skymizer

16:10 - 16:20