Pioneering AI with RISC-V – Built on Open Standards, Secured for Tomorrow
RISC-V 架構經過十年發展，在 AI SoC 領域展現強勁成長動能，並在晶片安全方面具有潛力。今年 RISC-V Taipei Day 首度於 COMPUTEX 台北國際電腦展舉辦，規模空前，包含四天主題館展示與 5 月 21 日的全日論壇，聚焦 AI 計算與安全應用趨勢。
隨著 AI 計算需求爆發，RISC-V 架構標準化與 AI 加速器（NPU、TPU）整合將提升效能，使 RISC-V SoC 可支援 AI 超算、優化訓練與推理，並強化邊緣 AI 運算，減少對雲端依賴，提高隱私與安全性。此外，RISC-V 開放架構允許開發者檢視晶片設計，降低安全漏洞風險，並可依需求擴充安全模組，增強防護能力。
RISC-V 具備開源與靈活客製化優勢，推動 AI 在雲端、邊緣 AI、自駕車、智慧醫療、AIoT 等領域的應用，並促進技術民主化，加速全球創新。台灣 RISC-V 聯盟 也將持續推動開源 AI 硬體與軟體生態，帶動 AI 晶片設計發展，共同見證 RISC-V 開創 AI 與安全運算新紀元。
隨著 AI 計算需求爆發，RISC-V 架構標準化與 AI 加速器（NPU、TPU）整合將提升效能，使 RISC-V SoC 可支援 AI 超算、優化訓練與推理，並強化邊緣 AI 運算，減少對雲端依賴，提高隱私與安全性。此外，RISC-V 開放架構允許開發者檢視晶片設計，降低安全漏洞風險，並可依需求擴充安全模組，增強防護能力。
RISC-V 具備開源與靈活客製化優勢，推動 AI 在雲端、邊緣 AI、自駕車、智慧醫療、AIoT 等領域的應用，並促進技術民主化，加速全球創新。台灣 RISC-V 聯盟 也將持續推動開源 AI 硬體與軟體生態，帶動 AI 晶片設計發展，共同見證 RISC-V 開創 AI 與安全運算新紀元。
RISC-V Pavilion @ COMPUTEX
Time: May 20-23
Location: L0425, 4F, Nangang Exhibition Hall 1
Location: L0425, 4F, Nangang Exhibition Hall 1
RISC-V Conference
Time: 09:00-17:00, May 21
Location: Room 505, 5F, Nangang Exhibition Hall 1
Location: Room 505, 5F, Nangang Exhibition Hall 1
精彩議程
報到與入場
Welcome Keynote:
Make RISC-V Popular in Taiwan for the World
林志明｜台灣RISC-V聯盟 會長, 晶心科技 董事長暨執行長
Taiwan is in the center of semiconductor, chip, IT, system design and manufacturing industries. From TSMC, Mediatek to Asus to Foxconn, there are so much business opportunity. IC design, manufacturing and application is the way to realize your value in Taiwan then export to the world no matter where you are based. Now RISC-V is experiencing this fantastic journey every day, more RISC-V IP, RISC-V based chips for various applications will be presented in this speech. RISC-V International Association (RVI) has done great job in raising RISC-V open standard with its ISA and specifications and eco-systems, so numerous application specific chips can been seen in the market, we encourage you to check out RISC-V IP if you are in chip design industry, or RISC-V based chips if you are in IT, OEM/ODM, system industries. Or, you will be excited to join in RISC-V ecosystem to provide your solution to the industries in Taiwan then the world. Supply chain based on RISC-V is so mature, now you should think about how to leverage it to win your success.
Welcome Remark
王其國 博士 | 台灣物聯網產業技術協會 理事長
The automotive and data center industries are experiencing a surge in the quantity and complexity of semiconductor content. Along with traditional performance, power, and area objectives, these markets also require dependability, which includes functional safety, reliability, and availability. Therefore, semiconductors for these applications must be both reliable, reducing their likelihood of failure, and resilient, improving their ability to recover from failure. This presentation reviews some of the challenges associated with achieving these objectives and explores how automation and standardization can play a vital role in meeting these new requirements.
Welcome Remark
巫建恒 | 數位發展部數位產業署簡正
Group Photo
RISC-V - To boldly go where no ISA has gone before
Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.
From its origins at UC Berkeley, led by pioneers like Krste Asanović and David Patterson, RISC-V emerged with a radical vision: instruction sets should be free. Today, that belief has propelled RISC-V beyond academia into a global force—open, standardized, internationally recognized, royalty-free, and highly extensible.
We have built a thriving ecosystem with growing membership and a maturing, complete architecture. But where do we go from here? The possibilities are boundless—custom silicon, vertical integration, AI-driven innovation, enhanced security, and full-stack solutions that redefine computing.
To get there, we must remain customer-focused and developer-first, ensuring RISC-V continues to break barriers. Join us as we explore the future of an ISA designed not just to compete but to revolutionize. The journey has just begun.
We have built a thriving ecosystem with growing membership and a maturing, complete architecture. But where do we go from here? The possibilities are boundless—custom silicon, vertical integration, AI-driven innovation, enhanced security, and full-stack solutions that redefine computing.
To get there, we must remain customer-focused and developer-first, ensuring RISC-V continues to break barriers. Join us as we explore the future of an ISA designed not just to compete but to revolutionize. The journey has just begun.
Tech Talk 1
蘇泓萌 博士 | 晶心科技 總經理暨技術長
RISC-V has rapidly gained traction across a wide range of applications, including automotive, 5G/networking, MCU/MPU, multimedia, storage, sensor processing, wearables, and wireless connectivity. Particularly prominent are emerging AI/ML applications from edge to cloud. As the RTOS, Linux, and Android ecosystems for RISC-V continue to mature, RISC-V cores are increasingly being used as main CPUs in embedded devices, personal computing and even servers. These advancements are significantly boosting RISC-V's market presence in the computing industry in the coming years.
In this talk, we will discuss four key elements in modern computing: namely AI/ML Accelerations, Embedded and Real-Time Processing, Safety and Security, and Application Processing. We will then show how the RISC-V architecture and ecosystem address them, using Andes solutions as examples.
In this talk, we will discuss four key elements in modern computing: namely AI/ML Accelerations, Embedded and Real-Time Processing, Safety and Security, and Application Processing. We will then show how the RISC-V architecture and ecosystem address them, using Andes solutions as examples.
Tech Talk 2
Luke Yen | Fellow of RISC-V CPU and Machine Learning Architectures
Tenstorrent
As artificial intelligence and autonomous systems become increasingly pervasive, the demand for scalable, high-performance, and open computing platforms is more critical than ever. This presentation outlines Tenstorrent’s approach to advancing RISC-V beyond its embedded roots into mainstream high-performance and automotive markets through mature IP and modular architecture. We introduce Tenstorrent’s RISC-V CPU roadmap, featuring the Ascalon and Callandor cores, designed for high SPECINT performance, and the Ascalon-Auto variant, which incorporates ISO 26262-compliant safety features for ADAS and autonomous driving applications. These processors are implemented using chiplet-based design and are paired with Tensix AI accelerators, enabling efficient support for AI workloads across edge devices, data centers, and automotive platforms.
Central to this platform strategy is the Open Chiplet Architecture (OCA)—a layered, open standard that facilitates interoperability across chiplets from different vendors. OCA standardizes interfaces across software, system management, transport, and physical layers, enabling modular, composable system integration and fostering a collaborative ecosystem for heterogeneous compute systems.
Together, these technologies represent a unified hardware-software strategy to support ubiquitous AI computing. They position RISC-V as a competitive, open alternative to proprietary architectures, ready to power the next generation of AI-enabled and automotive systems. This presentation underscores the role of openness, scalability, and performance in shaping the future of personalized and distributed intelligence through high-performance RISC-V platforms.
Together, these technologies represent a unified hardware-software strategy to support ubiquitous AI computing. They position RISC-V as a competitive, open alternative to proprietary architectures, ready to power the next generation of AI-enabled and automotive systems. This presentation underscores the role of openness, scalability, and performance in shaping the future of personalized and distributed intelligence through high-performance RISC-V platforms.
Skymizer HyperThought : Hyper-threading Language Processing Units for Large Language Model
唐文力 | 臺灣發展軟體科技股份有限公司 創辦人暨技術長
Large Language Models (LLMs) are rapidly becoming integral to a wide range of computing platforms—from data centers to smartphones and even microcontrollers. As interest in deploying LLMs across diverse systems grows, so does the need for domain-specific hardware acceleration. However, designing and implementing a hyperscale Language Processing Unit (LPU) introduces significant challenges. In this talk, we will explore key issues including hardware/software co-design, verification complexity, and SoC architecture exploration.
Lucky Draw
Lunch Break
報到與入場
透過開源協作釋放 RISC-V 的潛力
蔡傳資 | Chair of System Library Working Group, RISE
源自於對開放和協作的承諾，RISC-V 生態系統正在快速地演進。本次演講探討了 RISC-V 的發展動能，聚焦其超越 Arm 等現有架構的潛力，並強調動員其軟體生態系統的重要性。我們將深入研究促進這種成長的關鍵策略：加強協作和社區參與、投資基礎軟體堆疊組件以及致力於迭代性能優化。
本次演講將介紹 RISE 計畫，一項旨在推動開源軟體的創建、優化和上游化而令人興奮的合作。這些軟體將會被 RISC-V 生態系統有效地利用。 我們相信，RISC-V 為亞洲公司、尤其是台灣公司企業提供了絕佳的機會。透過硬體和軟體層面的創新，為客戶提供更高的價值。 本演講將討論一些具體範例，展示如何將為特定目的優化的硬體與開源技術結合，解鎖 RISC-V 的所有潛力，為未來鋪設由開放、協作和前瞻性技術所定義的道路。 為開放、協作和前瞻性技術定義的未來鋪平道路。
本次演講將介紹 RISE 計畫，一項旨在推動開源軟體的創建、優化和上游化而令人興奮的合作。這些軟體將會被 RISC-V 生態系統有效地利用。 我們相信，RISC-V 為亞洲公司、尤其是台灣公司企業提供了絕佳的機會。透過硬體和軟體層面的創新，為客戶提供更高的價值。 本演講將討論一些具體範例，展示如何將為特定目的優化的硬體與開源技術結合，解鎖 RISC-V 的所有潛力，為未來鋪設由開放、協作和前瞻性技術所定義的道路。 為開放、協作和前瞻性技術定義的未來鋪平道路。
RVA23 設定檔和平台規格對推動 RISC-V 生態系發展的重要意義
Mark Hayter |Rivos Inc. 共同創辦人兼首席策略官
標準 ISA 對於硬體和軟體生態系的發展至關重要，其可促進相容性、創新和採用。它們必須隨著時間的推移而發展，就像 x86 和 Arm 架構版本中的功能位元一樣。RVA23 設定檔代表了 RISC-V 架構的一項關鍵發展，它標準化了 64 位元應用處理器 ISA，以實現跨硬體設備的軟體可攜性。因此簡化了產品開發，並因二元程式碼的相容性，讓RISC-V廣泛應用在伺服器，汽車，及客戶端產品。本次演講將介紹 RVA23 對高性能應用處理器的影響，及其在不同應用場景的採用。
RVA23 設定檔引入了重要功能，包括 Vector 和 Hypervisor 擴展，旨在滿足高效能運算的需求。 Vector 擴展增強了 RISC-V 的平行資料處理，有利於機器學習和科學計算等工作負載。 Hypervisor 擴充功能支援伺服器虛擬化，支援可擴充且安全的雲端基礎架構和企業應用程式。
RVA23
設定檔的一個核心優勢是確保各種硬體實現的軟體相容性，從而能夠分發可在不同的 RISC-V 供應商之間運行的二進位套件。這對於 Linux 發行版（如 Ubuntu、RHEL）和 Android 尤其有用，其中應用程式以適用於所有用戶的二進位形式下載。 RVA23 設定檔定義了編譯器可以安全地為所有實用進行編譯的指令集。
完全啟用 Linux
發行版需要確定平台規格所提供的硬體和韌體功能。伺服器平台規格不僅描述了對 RVA23 設定檔的需求，還描述了伺服器 SoC 規格中的硬體需求以及引導和執行時間服務規格中的韌體詳細資訊。
對於開發 64 位元伺服器處理器的公司來說，採用 RVA23 設定檔和伺服器平台規格可確保一致的軟體分發、相容性和高效能。
RVA23 設定檔引入了重要功能，包括 Vector 和 Hypervisor 擴展，旨在滿足高效能運算的需求。 Vector 擴展增強了 RISC-V 的平行資料處理，有利於機器學習和科學計算等工作負載。 Hypervisor 擴充功能支援伺服器虛擬化，支援可擴充且安全的雲端基礎架構和企業應用程式。
RVA23
設定檔的一個核心優勢是確保各種硬體實現的軟體相容性，從而能夠分發可在不同的 RISC-V 供應商之間運行的二進位套件。這對於 Linux 發行版（如 Ubuntu、RHEL）和 Android 尤其有用，其中應用程式以適用於所有用戶的二進位形式下載。 RVA23 設定檔定義了編譯器可以安全地為所有實用進行編譯的指令集。
完全啟用 Linux
發行版需要確定平台規格所提供的硬體和韌體功能。伺服器平台規格不僅描述了對 RVA23 設定檔的需求，還描述了伺服器 SoC 規格中的硬體需求以及引導和執行時間服務規格中的韌體詳細資訊。
對於開發 64 位元伺服器處理器的公司來說，採用 RVA23 設定檔和伺服器平台規格可確保一致的軟體分發、相容性和高效能。
Revolutionizing AI Computing with World's First RISC-V 50 TOPS AI PC
Yuning Liang | Founder & CEO, DeepComputing
In the rapidly evolving world of artificial intelligence, breakthroughs in large language models (LLMs) are driving an unprecedented demand for high-performance AI computing devices—prioritizing local data privacy, security, and on-device AI processing.
At CES 2025, Nvidia showcased the future of AI-powered laptops with its GeForce RTX 50 Series, pushing AI-driven graphics and processing to new heights. Yet, a new frontier is emerging—RISC-V AI computing—ushering in an open, customizable era for AI hardware.
DeepComputing is leading this shift by developing the world’s first RISC-V 50 TOPS AI PC. This revolutionary device is built in collaboration with Framework, RISC-V SoC manufacturers, open-source OS leaders Canonical and Fedora, and AI innovators utilizing DeepSeek LLM models—powering AI applications like VLC Media Player and beyond.
This session will uncover how DeepComputing’s AI PC harnesses the open-source flexibility of RISC-V, enabling vertically optimized AI ecosystems. We’ll dive into the dual-die AI SoC architecture, the 64-bit RISC-V CPU with out-of-order execution, and how the system accelerates AI workloads—delivering faster inference, seamless AI app integration, and cloud-free AI experiences. Join us to explore how RISC-V + AI is not just a technological leap but a movement—pioneering a future of modular, sustainable, and developer-empowered AI computing.
At CES 2025, Nvidia showcased the future of AI-powered laptops with its GeForce RTX 50 Series, pushing AI-driven graphics and processing to new heights. Yet, a new frontier is emerging—RISC-V AI computing—ushering in an open, customizable era for AI hardware.
DeepComputing is leading this shift by developing the world’s first RISC-V 50 TOPS AI PC. This revolutionary device is built in collaboration with Framework, RISC-V SoC manufacturers, open-source OS leaders Canonical and Fedora, and AI innovators utilizing DeepSeek LLM models—powering AI applications like VLC Media Player and beyond.
This session will uncover how DeepComputing’s AI PC harnesses the open-source flexibility of RISC-V, enabling vertically optimized AI ecosystems. We’ll dive into the dual-die AI SoC architecture, the 64-bit RISC-V CPU with out-of-order execution, and how the system accelerates AI workloads—delivering faster inference, seamless AI app integration, and cloud-free AI experiences. Join us to explore how RISC-V + AI is not just a technological leap but a movement—pioneering a future of modular, sustainable, and developer-empowered AI computing.
RISC-V accelerating the future of AI & Automotive computing
Nathan Ma | AVP of Marketing and Strategy, Nuclei System Technology
RISC-V is revolutionizing computing paradigms across AI and automotive applications, offering an unprecedented combination of architectural flexibility, scalability, customization and cost efficiency. In AI applications, RISC-V's modular design enables customized acceleration for AI innovations both for edge & cloud, while in automotive systems, its openness facilitates the trend of software defining vehicles.
As a leading RISC-V processor IP provider, Nuclei's RISC-V products have been adopted across diverse applications, from AI accelerators to automotive MCUs/SoCs. Nuclei is the world's first RISC-V IP company to achieve ISO26262 ASIL-D product certification. This achievement not only validates our technological capabilities but also demonstrates RISC-V's readiness for the most demanding safety-critical applications.
In this presentation, we will share our hands-on experience in developing and deploying RISC-V solutions for AI and automotive applications. We'll provide in-depth technical insights into:
As a leading RISC-V processor IP provider, Nuclei's RISC-V products have been adopted across diverse applications, from AI accelerators to automotive MCUs/SoCs. Nuclei is the world's first RISC-V IP company to achieve ISO26262 ASIL-D product certification. This achievement not only validates our technological capabilities but also demonstrates RISC-V's readiness for the most demanding safety-critical applications.
In this presentation, we will share our hands-on experience in developing and deploying RISC-V solutions for AI and automotive applications. We'll provide in-depth technical insights into:
- Our RVV1.0 vector extension implementation supporting up to 1024-bit VLEN & DLEN, optimized for the offloading of specific AI layers or operators
- We'll also share some successful cases in both AI acceleration and automotive computing.
以 RISC-V 架構打造 AI 與後量子安全融合的自主機器人平台
池明洋 | 池安量子資安股份有限公司 創辦人&董事長暨執行長
在 AI 驅動的自主系統迅速演化之際，後量子時代的資安威脅正同步升級。本場演講將介紹 Chelpis 團隊針對下一世代機器人所設計的 RISC-V AI + PQC 晶片架構，如何在邊緣裝置中結合 AI 運算、感測器融合與後量子加密，打造一個可信、自主、安全的機器人運算核心。
涵蓋範圍包括工業用仿生機器狗、自主無人機、智慧物流協作機器人等實際應用案例，並深入探討台灣在全球 AI 安全運算與量子防護晶片領域的戰略定位與發展機會。
Enabling NPU AI Compute entirely on RISC-V ISA
Roger Espasa | Founder & CEO, Semidynamics
In recent deployments, RISC-V has been used in AI applications, primarily for controlling or supporting AI algorithms. To address NPU applications, custom hardware has traditionally been placed adjacent to the RISC-V CPU, effectively shifting the pre-RISC-V proprietary accelerator approach into the RISC-V ecosystem—bringing the same legacy restrictions into the open ISA RISC-V world.
Semidynamics' novel approach eliminates this issue by introducing a RISC-V ISA-only, performance-optimized compute engine that integrates CPU, vector, and tensor operations into a single compute element. This innovation enables RISC-V to enter the previously unaddressed NPU marketplace. With configurable performance ranging from 8 to 64 TOPS, this RISC-V engine delivers efficient AI acceleration for LLMs, deep learning, edge AI, and datacenters.
Semidynamics' novel approach eliminates this issue by introducing a RISC-V ISA-only, performance-optimized compute engine that integrates CPU, vector, and tensor operations into a single compute element. This innovation enables RISC-V to enter the previously unaddressed NPU marketplace. With configurable performance ranging from 8 to 64 TOPS, this RISC-V engine delivers efficient AI acceleration for LLMs, deep learning, edge AI, and datacenters.
Panel Discussion
主持人:
曲建仲 博士 | 知識力科技 執行長
與談人:
Frankwell Lin | Chairman, RISC-V Taiwan Alliance
Lu Dai | Board Chair, RISC-V International | Senior Director of Technical Standards, Qualcomm Technologies, Inc.
Dr. Charlie Su | President and CTO, Andes Technology
Luke Yen | Fellow of RISC-V CPU and Machine Learning Architectures, Tenstorrent
William Wei | CMO and EVP, Skymizer
Lucky Draw
賦歸與交流
貴賓介紹
贊助夥伴
Platinum
Golden
Silver
Special Partner
聯絡我們
Organizer
Co-organizer
