Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces general availability of the high-performance AndesCore™ AX65 out-of-order superscalar multicore processor IP. The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with 13-stage pipeline, 4-wide decode, 8-wide out-of-order execution, AX65 targets the Linux application processor sockets of computing, networking, and high-end controllers. It also received “Best IP/Processor of the Year” Award from EE Times Asia last December.
Andes has been very successful on the embedded controllers and high-performance AI vector processors. As RISC-V ecosystem for Linux is getting matured, the demand for high-performance RISC-V processors for general-purpose applications rises. Andes takes this opportunity to introduce the AX65 to complete its comprehensive CPU lineup, spanning from low-power embedded solutions to high-end Out-of-Order processors. Customers who develop complex SoC can now use AX65 as the primary Linux application processor, the AX45MPV/NX27V for the vector/DSP processing and the N25/N225 processors as the resource and power manager. Leveraging the entire range of CPUs in the AndesCore™ families enables customers to streamline their development process, benefit from integrated support, and significantly reduce development cost.
The AX65 operates at speeds exceeding 2.0GHz on a 12nm process, boasting a SpecInt2006 score of 8.25 per GHz — outperforming the Cortex A75 with an efficient memory hierarchy. It also supports up to 8-core cache coherence with maximum 8MB shared cache. The AX65 is fully compliant with the RISC-V RVA22 profile, ensuring compatibility with operating systems and software within the RISC-V ecosystem. On the security side, AX65 supports Enhanced PMP (ePMP) for further securing memory accesses, and K (scalar cryptography) extension for accelerating AES and SHA crypto operations. For running Linux OS, the AX65 supports VIPT L1 instruction cache, SV48 virtual address space, and 2-level TLB with simultaneous hardware page walkers. It also incorporates state-of-the-art branch prediction mechanism with TAGE-L algorithm, return address stack and 2-level branch target buffer. The AX65 can be used as an application processor in networking applications like Wi-Fi, 5Gnr, and O-RAN, as well as in edge computing and industrial PCs. Furthermore, it is well-suited for serving as the primary controller processor in embedded applications.
“AX65 is our first out-of-order processor. It brings over 100% performance boost on SPECint2006 over the popular 45 Series processors. The successful launch of AX65 marks a quantum leap in performance of our processor lineup. With this proven OoO architecture, we can now target additional high-performance opportunities such as the main processors in AI/ML, Multimedia, Networking and Storage. That is very exciting for Andes,” said Dr. Charlie Su, President and CTO of Andes Technology.
“Among the RISC-V IP vendors, Andes delivered the first DSP-capable processor in D25F, the first vector processor in NX27V as well as the first functional safety processor with full ISO 26262 compliance in N25F-SE, and now they are all very successful in the market. Even though we are not the first for the out-of-order processor, we released it with a solid pace so that we do not need to reshuffle our teams along the way. Customers can trust Andes as a long-term supplier and partner for all their RISC-V CPU needs,” said Frankwell Lin, Chairman and CEO of Andes Technology.
Early customers in Asia, Europe and USA have been evaluating AX65 since August. Customers in multimedia and AI/ML have already signed up. The AX65 with Linux and RTOS support as well as development tools is available immediately for general licensing.