In recent years, the RISC-V architecture has gained significant traction amongst a wide variety of chipmakers. It may be less than a decade since the first RISC-V workshops were held, but today the open architecture is finding its way into a myriad of chips and technologies industry-wide. It was just a couple of weeks ago when tech giants Google and Qualcomm announced they’d be teaming up on a RISC-V based Snapdragon Wearable Platform for future Wear OS devices, and today – with the RISC-V Summit currently underway in Santa Clara – silicon design, verification and IP leader Synopsys has announced an array of new 32-bit and 64-bit ARC-V Processor IP targeting embedded automotive, storage, and IoT applications. The IP includes the Synopsys ARC-V RMX (Ultra Low Power Embedded, 32-bit processor), the ARC-V RHX (Real-Time, 32-bit), and the Synopsys ARC-V RPX (64-bit multi-core host processor).
Synopsys is well known for its leadership role in the EDA (Electronic Design Automation) space, where its AI-infused toolset is leveraged across the industry by silicon kingpins like Intel, NVIDIA and AMD, and fledgling startups alike. And RISC-V is an open standard Instruction Set Architecture (ISA) maintained by RISC-V International. RISC-V is often viewed as an alternative to other licensable architectures, like Arm for example, but due its open-source licensing model, customization flexibility, and (typically) lower cost, RISC-V offers a number of key advantages.