Latest Ratifications Primarily Target Core Areas of Efficiency, Vector, and Virtualization
ZURICH – April 4, 2024 –
RISC-V International, the global standards organization, today announced that 40 new technical specifications have been ratified in the past two years, adding to an extensive list of ratified RISC-V specifications. Primarily addressing three core areas, Efficiency, Vector, and Virtualization, these new specs cement the RISC-V instruction set architecture (ISA) as one of the top three ISAs available today.
Across markets such as aerospace, AI/ML, automotive, data center, embedded, HPC, and security, companies are building innovative, customized, and scalable RISC-V solutions with the support of newly released RISC-V specifications and supporting extensions. Currently, there are more than 13 billion RISC-V cores in the market, and the ratification of these new specs further enables the growth and adoption of RISC-V implementations worldwide.
RISC-V is a standard ISA and allows members the freedom and flexibility to use RISC-V how they see fit. RISC-V International is the steward of the RISC-V standard and includes 75 technical working groups collaborating on standard specifications to advance the adoption of the RISC-V ISA. Each extension and spec must undergo a rigorous development, review, and approval process before it can be ratified.
“As chair of the Technical Steering Committee and an active participant on several RISC-V technical working groups, I know first-hand the power of collaboration and its impact on the impressive technical achievements the RISC-V International community have accomplished,” said Greg Favor, chair of the Technical Steering Committee and co-founder and CTO of Ventana Micro Systems. “Organizations – both public and private – around the world are turning to RISC-V because of its elegance and simplicity. The base RISC-V ISA is simple and locked. The extensions and new specs ratified are a direct response to membership priorities and industry needs.”
Top specifications include:
- Efficiency: bitmanip, Zc*, Zfa
- Virtualization: hypervisor, aia, iommu
- Vector: vector, vector crypto, FP16, BF16
These ratifications coupled with recent advancements in the RISC-V software ecosystem such as the formation of RISE and the software optimization guide, show continued progress. The entire RISC-V ecosystem benefits from a shared standard ISA, with design freedom, flexibility, interoperability, and scale. RISC-V International has a diverse membership base, with about one-third of the members in North America, one-third in Europe, and one-third in APAC. The collective investment and shared contributions of tens of thousands of engineers across more than 4,200 members ensure that RISC-V is already the accepted standard ISA in compute for generations to come.
“The RISC-V pace and breadth of innovation is truly impressive! Our community is driven by the power of innovation and collaboration that only a multitude of engineers can bring to ensure the technical building blocks of RISC-V withstand the test of time,” said Calista Redmond, CEO of RISC-V International. “Our open collaboration and dedicated technical community enable broad global adoption and participation, accomplishing significant and strategic technical ratifications in a short period of time.”
RISC-V International is committed to advancing the RISC-V ISA and pushing the technical boundaries of hardware and software design. In 2024, RISC-V anticipates the ratification of its Profile family and the ecosystem’s first Platform delivering increased portability in software design. For more information check out RISC-V Exchange, RISC-V Ecosystem Landscape, and the RISC-V Profiles Specification.