RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), highlighted the organization’s incredible year of growth in a keynote today by Calista Redmond, CEO of RISC-V International, at the RISC-V Summit, which is being held virtually from Dec. 8-10, 2020. This year RISC-V International has made significant progress on technical deliverables, launched new educational programs, expanded its leadership team and membership base, and has continued to see strong commercial adoption.
“RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, SoCs, developer boards, software and tools across computing from embedded to enterprise,” said Redmond. “We’re proud of our growing global membership, which has more than doubled in the last year to 1,000 total members, including 222 organizations.”
In 2020 RISC-V continued to focus on driving progression and closure on standards and technical deliverables. In March, the RISC-V Processor Trace Task Group ratified the processor trace specification, a new standard trace encoder algorithm that allows engineers and developers to see exactly what instructions a core is executing, step by step. The RISC-V Technical Steering Committee (TSC) focused on implementing organizational governance practices to increase transparency. The RISC-V Architecture Test Working Group initiated a compatibility framework and tests to help developers ensure their solutions are in accordance with the specification. Additionally, RISC-V International and GlobalPlatform, the standard for secure digital services and devices, announced a partnership to help accelerate the development of open standards that simplify security design for hardware developers and enhance the security of Internet of Things (IoT) devices and processors. RISC-V anticipates the Q1 2021 public review for our Vector, Bit Manipulation, Scalar Cryptography, Packed SIMD, Secure PMP and Virtual Memory extensions. RISC-V is also creating a security response process to better respond to potential security issues and innovative cryptography extensions to enhance performance in secure deployments.
RISC-V International has cultivated alliances with 16 different regional and industry groups to ensure collaboration across all boundaries and interests. Three of these projects, which are already in motion, include: China Academy of Sciences and PLCT Lab are working on low level virtual machine (LLVM) and GNU Compiler Collection (GCC) projects for unprivileged instructions; Shakti and IIT Madras are working on architecture tests for unprivileged instructions; and the RISC-V International Open Source Laboratory (RIOS Lab) are working on both the formal model and architecture tests for privileged instructions.
In June 2020, RISC-V International appointed Mark Himelstein as CTO to work with the RISC-V technical community to understand, define and lead strategic imperatives from ISA extensions to software and from embedded to high performance computing (HPC), with all members’ interests in mind. The organization further expanded its leadership team with the appointment of Kim McMahon as Director of Marketing to increase the visibility of RISC-V and amplify the growing industry momentum of our member community. RISC-V International also announced the first class of RISC-V Ambassadors this year. Ambassadors are RISC-V technical experts from around the world who work together with RISC-V to engage engineers around the world in technical forums.
Said Himelstein: “RISC-V has been laser focused on ratifying extensions, identifying and addressing opportunities and gaps, and expanding collaboration and development across markets to strengthen the community and access to RISC-V resources. In 2020 we’ve expanded the number of technical groups, forged new alliances and rolled out new educational programs to help accomplish this goal, and will continue to double down on these efforts to help fuel volume deployments of RISC-V in the coming years.”
RISC-V International has launched three new learning programs including the RISC-V Training Partner Program, Learn online, and university alliances to extend the breadth and reach of RISC-V knowledge, provide opportunities for a broader audience to teach and learn, and engage the community to achieve expertise in the critical areas needed for a healthy ecosystem. One of the courses that was recently unveiled is the Imagination University Programme (IUP) course “RVfpga: Understanding Computer Architecture.” The course is currently available in English, and a Chinese version will be available in early 2021. Students and developers interested in RISC-V can also check out more than 30 educational courses on RISC-V offered from universities and other educational providers from around the world.
This year the RISC-V community has continued to contribute to RISC-V projects, collaborate together and commercialize RISC-V hardware and software solutions. RISC-V also launched the RISC-V Exchange with more than 124 RISC-V cores and SoCs and Developer Boards along with 129 RISC-V software applications and tools.
Notable examples of RISC-V adoption in 2020:
- Alibaba unveiled its RV64GCV core that will be used for its Xuantie 910 processor aimed at cloud and edge servers.
- Andes released new superscalar multicore processors and processors with Level-2 (L2) cache controller.
- BBC Learning and Tynker released the BBC Doctor Who HiFive Inventor to engage the next generation of coders.
- Bluespec, Inc. unveiled RISC-V Explorer, a fast, free and accurate way to evaluate RISC-V cores.
- CHIPS Alliance announced new enhancements to the SweRV Core EH2 and SweRV Core EL2.
- C-DAC selected Valtrix STING for design verification of RISC-V based microprocessors.
- Codasip released three new RISC-V application processor cores providing multi-core and SIMD capability.
- De-RISC developed the first version of its De-RISC MPSoC platform and Performance Monitoring Unit as part of its effort to create a RISC-V platform for the aerospace market.
- Esperanto Technologies unveiled an accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.
- Espressif launched cost-effective microcontroller with Wi-Fi and Bluetooth LE 5.0 connectivity for secure IoT applications.
- GreenWaves Technologies announced its ultra-low power GAP9 hearables platform that enables scene-aware active noise cancellation and neural network-based noise reduction.
- Huami released a new AI chip for biometric wearables.
- IAR Systems partnered with GigaDevice to deliver powerful development tools for GigaDevice’s RISC-V based microcontrollers.
- IAR Systems and SiFive enhanced support for the SiFive Insight solution in IAR Embedded Workbench to bring leading debug and trace capabilities to the RISC-V community.
- Imagination Technologies partnered with RIOS Laboratory to enable RIOS Lab to build a complete development platform and open-source ecosystem for RISC-V single-board computers.
- Imperas Software debuted a reference model with UVM encapsulation for RISC-V verification.
- Lynred and GreenWaves Technologies collaborated on a new Occupancy Management Reference Platform for people counting sensors.
- MEEP developed Coyote, a performance modeling tool to provide an execution-driven simulation environment for multicore RISC-V systems with multi-level memory hierarchies.
- Menta and Andes announced a partnership enabling hardware reconfiguring for ISA extension.
- Mentor collaborated with Imperas on RISC-V core RTL coverage driven design verification analysis.
- Microchip Technology announced a RISC-V-based SoC FPGA development kit to accelerate customer design deployment and commercial adoption across a variety of industries.
- Micro Magic, Inc. unveiled a 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V.
- NeuLinker selected Codasip’s Bk5 core and the Codasip Studio customization toolset for its security and AI-powering solutions.
- OneSpin announced it is contributing its processor integrity solutions for the German government’s ZuSE-Scale4Edge project to assure integrity of edge computing processors.
- OpenHW Group implemented Imperas RISC-V reference models for coverage driven verification of open source CORE-V processor IP cores.
- PINE64 unveiled the Pinecil TS100 compatible soldering iron.
- SiFive introduced HiFive Unmatched! to make it easy for developers to build a RISC-V PC.
- SYSGO and Cobham Gaisler announced a collaboration to deliver SYSGO’s hypervisor-based real-time operating system, PikeOS, ported onto Cobham Gaisler’s IP cores NOEL-V and LEON.
- Telink Semiconductor announced its TLSR9r SoC series for wireless audio, wearable devices and other cutting-edge IoT applications.
- The European Processor Initiative finalized the first version of its RISC-V accelerator architecture, named EPAC.
- Think Silicon introduced new inference micro GPU architecture suitable for AI-Vision and graphics tasks.
- University of Chinese Academy of Sciences (UCAS) developed NutShell, a 64-bit SoC which operates at up to 200MHz and can run Linux.
- zGlue teamed up with Antmicro and Google in open chiplet initiative to create a more open and collaborative ASIC design ecosystem.
- In March 2020, RISC-V International was incorporated in Switzerland. As part of the move, RISC-V shifted to a new, more inclusive membership structure. RISC-V International is a truly global organization, with 31 percent of its membership base in North America, 33 percent in Europe and 37 percent in Asia-Pacific. To engage with the global RISC-V community, RISC-V International has participated in nearly 40 events ranging from Embedded World and HiPEAC in Europe to DAC and Open Source Summit in North America to regional events in China and Taiwan.