To enable SoC design teams and Automotive software developers to build optimized and certifiable software solutions.
Munich, Germany – March 27, 2024 –
TASKING proudly announces that its ISO 26262 (functional safety) and ISO/SAE 21434 (cybersecurity) compliant compilers now fully support the Andes FuSa certified RISC-V IP. This advancement expands TASKING’s RISC-V tool suite to include compilation, debugging, performance tuning, timing, and coverage analysis tools, providing a comprehensive solution for automotive systems development.
This milestone signifies a significant stride in empowering SoC design teams and automotive software developers to craft highly optimized and certifiable RISC-V based solutions. The newly introduced RISC-V compiler, compliant with ASIL D standards, seamlessly supports both current and forthcoming FuSa certified Andes RISC-V cores. Noteworthy is the compiler’s adaptability to the RISC-V ISA and its extensions, including Andes-specific extensions, ensuring dynamic optimization tailored to the target device, thereby enhancing efficiency and performance.
Andes Technology has achieved remarkable milestones in the automotive market with the introduction of the world’s first RISC-V ISO-26262 fully compliant core, N25F-SE, in 2022. Subsequently, Andes is about to unveil the ASIL-B certified D25F-SE equipped with the RISC-V SIMD/DSP P-extension support (draft), enabling efficient processing of multiple data in a single instruction. Looking ahead, Andes is set to launch processors meeting the ASIL-D standard, including the compact and secure D23-SE, the high-performance D45-SE, and the forthcoming ADAS-capable core in AX60 Series. These advancements underscore Andes’ ability to provide tailored solutions for diverse automotive applications, highlighting its leading expertise in the automotive RISC-V IP market.