Hsinchu, Taiwan – Oct 22, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.
The D45-SE, derived from the production-proven D45, is a 32-bit, 8-stage dual-issue processor that supports the RISC-V GCBP extensions, including single/double precision FPU, 16-bit compression, bit manipulation, draft of packed SIMD/DSP extensions, and the Andes performance enhancements. Furthermore, it incorporates numerous safety features, such as dual-core lockstep (DCLS), a real-time diagnostic safety circuit that utilizes an additional processor and a set of comparators to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to secure bus transactions; a core trap status bus interface that provides real-time trap status information from the core; and StakSafe™, a hardware mechanism that protects the stack, and maintains the same outstanding 6.12 Coremark/MHz as the D45. With these safety enhancements, the D45-SE ensures fault tolerance that meets the rigorous demands of safety-critical applications.