HSINCHU, TAIWAN – October 17, 2022 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announces its safety-enhanced AndesCore® N25F-SE is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications. SGS-TÜV Saar GmbH, an independent functional safety certification body, has assessed and completed product audit process for N25F-SE with achieved functional safety for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9.
AndesCore® N25F-SE. The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size. The efficient 5-stage pipeline of the N25F-SE provides a good balance of high operating frequency and compact design. Its flexible interfaces greatly simplify SoC designs. Like its sought-after cousin the N25F, the N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.
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