2024 RISC-V Taipei Day

精彩議程

9/10 DVCon Taiwan
9/11 RISC-V Taipei Day

Track 1
Track 2

09:00 - 09:30

Welcome

09:30 - 09:40

Opening

DVCon Taiwan 2024 Steering Committee

09:40 - 10:10

Keynote 1: May the Dependability Be with You: Reliability and Resilience Challenges in SoC Design

Alessandra Nardi PhD | Chair, Functional Safety Working Group, Accellera (Executive Director, System Solutions Group, Synopsys)

The automotive and data center industries are experiencing a surge in the quantity and complexity of semiconductor content. Along with traditional performance, power, and area objectives, these markets also require dependability, which includes functional safety, reliability, and availability. Therefore, semiconductors for these applications must be both reliable, reducing their likelihood of failure, and resilient, improving their ability to recover from failure. This presentation reviews some of the challenges associated with achieving these objectives and explores how automation and standardization can play a vital role in meeting these new requirements.

10:10 - 10:40

Keynote 2: Not Your Father’s Formal Verification

Erik Seligman | Sr. Product Engineering Architect, Cadence

10:40 – 11:10

Keynote 3: Empowering Design and Verification with AI / ML

Chilai Huang | Senior Director, R&D, Siemens

The electronics industry is on the cusp of a transformative paradigm shift. In 2023, AI/ML-focused chips comprised 20% of the semiconductor market, a figure projected to soar to 73% by 2030, driven by the relentless pace of digital transformation. In parallel, single-chip SoCs are no longer sufficient – muti-chip 3DIC designs are required to meet customers’ compute requirements.

Traditional design flows, which rely on disparate point tools for optimization, will struggle to meet the demands of these emerging systems. Hence, within the context of the new 3DIC design and verification landscape, this keynote will describe how to leverage integrated, AI/ML-powered D&V technology to get the necessary step-function productivity improvements for these complex projects.

11:10 – 11:30

Morning Break

11:30 - 12:30

Panel Discussion: AI for Formal Engineering and Formal Engineering for AI – What catches up fast?

Moderator: Chung-Yang (Ric) Huang | Professor, EE, NTU
Panelist: Sandeep Jana | Sr. Director, VC Formal R&D, Synopsys
Panelist: Chilai Huang | Senior Director, Avery R&D, Siemens
Panelist: Chris Komar | Sr. Product Engineering Group Director, Cadence

12:30 - 13:30

Lunch Break

13:30 - 13:50

Nitin Kishore | Truechip

13:50 - 14:10

Improving UVM test benches using UVM Run time phases

Lingkai Shi & Prosper Chen | AMD

14:10 - 14:30

Solving Memory Configurations Challenge with SVRAND Verification Flow

Krunal Kapadiya | Cadence

14:30 - 14:50

The RTL-Level SDC Timing Exception Verification

ChienLin Huang | MediaTek

14:50 - 15:10

Afternoon Break 1

15:10 - 15:30

Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices

Gopi Srinivas Deepala | Silicon Interface

The papers demonstrates a solution for the work around using higher memory locations in PCIe for single calls to the configuration address and data I/O ports CF8 and CFC (intel chip set IO ports); the issues on data integrity and security is further compounded when multiple CPUs are connect to the Bus0 of the Root Complex! Memory management using Address Space, Address Regions and Traits, as well as Byte Addressability on PCIe particularly in multi-Core environment wherein several CPUs or Cores may accesses data from Memory through the Root Complex Hub using CF8 and CFC ports and successfully addressing data integrity and security issues To prevent such issues and safeguard device data, we leveraged the features of PSS v2.0 like replicate and repeat , constraint for all and many more implement to access to CF8 and CFC addresses and data signals when multiple devices access CPU system memory for data threading, parameterized traits, resource sharing and locking ensure proper synchronization, preventing race conditions. Further, allocation of the Address Space region (Contiguous Byte Addressable) for TYPE0 or TYPE1 Configuration memory space (256 bytes to 4Kbytes extended configuration space) is achieved using Byte Addressability. PCIe devices claim this Configuration Space region (256 to 4kbytes) for operation when needed, utilizing an allocation trait size 1K bytes to define and match regions. Configuration Space with traits that satisfy the claim’s trait constraints is the candidate for matching regions. Through this approach, we provide clarity on our proposal while highlighting the practical implications for enhancing memory management and data protection in PCIe devices.

15:30 - 15:50

Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS)

Luther Kai Xuan Lee | Andes

To accommodate the wide range of applications, AndesCore processors provide comprehensive configuration options to meet various requirements. However, this configurability introduces a significant challenge in verification processes, particularly in generating various test scenarios. These scenarios include instruction execution with pipeline hazards or instruction decoding with versatile configurations. The Portable Testing and Stimulus Standard (PSS) introduced a domain-specific language (DSL) for describing test scenarios, enabling the automatic creation of multiple test scenarios. Nonetheless, the current PSS-based test generation tools, typically vendor-derived, require licensing fees and primarily cater to system verification rather than processor verification.

To address these limitations, we developed a PSS-based test generation tool for verifying AndesCore processors. Its efficacy is demonstrated through two case studies: 1) pipeline forwarding, and 2) instruction decoding for vector extension. Notably, we made this tool openly available on GitHub, fostering transparency and community engagement.

15:50 - 16:10

Left-shifting Testbench Development Using Environment Inversion in UVM

Yu-Ju Su | Synopsys

Minimizing time-to-market is crucial for hardware verification engineers. The Universal Verification Methodology (UVM) offers testbench modularity and reusability which significantly improves testbench development efficiency. However, UVM’s effectiveness is still restricted by design readiness. Conventional approaches require a design before testbench bring-up and thus creates a bottleneck. This paper proposes the Environment Inversion Methodology, a novel approach that leverages UVM’s framework while overcoming the dependency on design. We introduce the Design Under Test Double (DUTD), a virtual representation of the design seamlessly integrated within the UVM environment. This enables comprehensive verification activities even before the actual design is in place.

16:10 - 16:30

Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores

Yu-Tse Huang | Andes

This paper presents a formal verification approach: utilizing ISA-Formal techniques to verify a commercial RISC-V out-of-order (OOO) CPU pipeline.
We reveal three major steps to provide convincing results.
1. A reusable ISA model generated from Sail RISC-V.
2. A pipeline follower to collect information from design.
3. An universal assertion to make sure the RTL produces the same result as predicted.

First, we demostrate the steps of using Sail RISC-V formal model with custom codes (e.g., RAM read and write functions) to create reusable instruction models. Secondly, we leverage the reorder buffer (ROB) structure to create a CPU pipeline follower to extract essential information, such as general purpose registers (GPRs) states, and system control state registers (CSRs).

Finally, we describe the implementation of the one-cycle assertion model to setup the ISA formal check. We adopt the ISA formal approach proposed by Alastair Reid and etc. [1], on a high-end OOO CPU design. The result not only shows the capability of formal verification but also highlights the importance of a strong formal model for RISC-V ecosystem. In this paper, we demonstrate a design bug, which was found immediately by adding new CSRs to the Sail model, proves the power and effectiveness of this solution.

16:30 - 16:40

Afternoon Break 2

16:40 - 17:00

Award

Philip Tsai | GUC

Jimmy Liu | NYCU

13:30 - 13:50

The ASIC Renaissance – A glance into the future SoC enablement

Kurt Huang PhD | TESDA

As we approach a new era of chip development, ASIC full custom is in higher demand than ever before. In this topic, Kurt is going to discuss how the rise and challenges of ASICs contribute to development in most sectors, ranging from automotive to AI. Uncover the existing trends, how they are likely to impact the ASICs, and how this impact is projected to revolutionize SoC design.

13:50 - 14:10

Trojan Horse Detection for RISC-V Cores Using Cross-Auditing

Siang-Cheng Huang | NTHU

In security-critical applications, malicious Trojan Horses embedded in a CPU core could impose great threats on the security of an SoC. In this work, we propose a “Trojan-Horse detection framework” using a cross-auditing scheme. Our framework takes a target RISC-V core, and then pairs it up with another reference RISC-V core to conduct the functional simulation using a set of benchmark programs. The “care outputs” of both cores are compared to reveal the potential Trojan Horses in the target core. A set of well-known Trojan Horses are implanted into an open-source RISC-V core to evaluate the effectiveness of this framework. We found that we can successfully detect almost every implanted Trojan Horse as long as it has been activated and manifested by the benchmark programs.

14:10 - 14:30

Integrated verification ecosystem for regression management, coverage convergence, and debug automation

William Huang | Synopsys

To speed up turnaround time of verification flow, various EDA tools have been introduced to automate and accelerate different aspects in the flow, including regression management, coverage optimizer for saturation and diversity, coverage hole analysis, automatic binning of failure cases, and root cause prediction and analysis.

Although each tool handles its respective field well, they can be further integrated to construct a comprehensive verification automation ecosystem by automatic connection and data utilization between tools. In this paper, we’ll introduce how the proposed verification automation ecosystem can facilitate user’s daily tasks in the verification flow.

14:30 - 14:50

Conquering UCIe 1.1 Multi-die System Verification Challenges

Varun Agrawal | Synopsys

The Universal Chiplet Interconnect Express (UCIe) v1.0 standard was introduced in March of 2022 and v1.1 was published in July 2023. There is a huge demand for an open chiplet ecosystem that will unleash innovation across the compute continuum which in turn increases the demand for power efficient and cost-efficient solutions.

UCIe 1.1 addresses four broad areas that encourage a thriving open chiplet ecosystem. These include enhancements like automotive segment, streaming protocol usages, cost optimization for advanced packages, and compliance testing.

This session focuses on key design considerations to bring forward the verification requirements and an overview of verification solution to enable UCIe 1.1 complex designs.

14:50 - 15:10

Afternoon Break 1

15:10 - 15:30

Enable power-aware UPF emulation on Palladium

Nan-Shing Lee | MediaTek

Cheng-Yuan Shueh | Cadence

Unified Power Format (UPF) or IEEE 1801 is a standard format by IEEE for specifying all design and technology-related power constraints for low-power chip.

To achieve completed verification of power architecture and low-power functionality, MTK has realized the engagement of power structure on Palladium especially on unplugged products. With strong debugging capability of Palladium, UPF compilation and related verification on emulation environment became very easy. Palladium models the supply network, power off-on, corruption, isolation, and retention in the emulation netlist image, which is generated from the RTL files and 1801 files. Additionally, Palladium also satisfied MTK with customized requirements such as special UPF syntax supporting, customized model behavior development, collaboration of special RTL and UPF structure for more complicated application and better cooperation.

15:30 - 15:50

Augment and Automate Formal for Designers

Kanwar Pal Singh | Cadence

This tutorial explains the various Formal enabled checks/verification capabilities which can be used by designers. It also describes how these can be easily deployed when these are integrated in the RTL Designer’s regular check-in, regression and milestone signoff tasks.

15:50 - 16:10

Better Late Than Never – Collecting Coverage From Ones and Zeroes

Tsungyu Tsai | Siemens

This paper lays out a flow and strategy to read a test vector file of ones and zeroes captured from simulation, emulation, tester or elsewhere, and then applies those test vectors to a SystemVerilog coverage model and generates coverage reports. This technique can help understand the coverage that is represented by the captured tests – the ones and zeros.

16:10 - 16:30

A Comprehensive Data-Driven Function Verification Process

Tsungyu Tsai | Siemens

As Machine Learning (ML) technology is all the rage these years, data collection has become one of the keys to daily work. The increasingly complex designs will no longer be a problem with the help of ML technology. We can apply ML technology on getting the scenarios/checkers that mapping to the test-plan, testcase analysis, coverage closure, prediction or identification of error causes, and presentation of verification results. In order to have enough big data for ML to obtain accurate inferences, a complete process for function verification becomes crucial. In this paper, we propose a complete process that includes each stage of function verification and a method of collecting relevant data. By applying this process, the collected data can be perfectly applied to various applications. And this process is compatible with different verification methods, including dynamic simulation and static analysis.

Track 1
Track 2

09:30 - 09:45

RISC-V: More Than AI

Mr. Frankwell Lin｜Chairman, RISC-V Taiwan Alliance (Chairman and CEO, Andes Technology)

RISC-V penetrated all aspects of application, including but not limited to AI. In this report, RISC-V application will be discussed, AI, certainly, but also Application processor, High performance Computing, Data Center, Storage, Automotive, Networking, Personal Computing, IoT, 5G, and so on. The base is RISC-V fast evolution of its ISA extension, specifications, and features. RISC-V International Association also promoted RISC-V to all over the world. In terms of value chain, RISC-V based SoC will start to penetrate OEM and ODM, since major world brands joined in, that lead the wave of RISC-V adoption. Many RISC-V eco-system, IP and chip providers join in 2024 RISC-V Taipei Day event, to jointly develop and contribute to tomorrow's plan of Taiwan's industry value.

09:45 - 09:50

Welcome Remark

Dr. Alex Wang｜Chairman, Taiwan IoT Technology and Industry Association, TwIoTA

09:50 - 09:55

Welcome Remark

Inviting Government Representative

09:55 - 10:00

Group Photo of Speakers

10:00 - 10:15

Architecture of Choice for AI

Lu Dai｜Board Chair, RISC-V International

10:15 - 10:35

Leveraging RISC-V Solutions for Intelligence Everywhere

Dr. Charlie Su｜President and CTO, Andes Technology

While the rising RISC-V architecture has been adopted in applications such as automotive, connectivity, 5G, networking, storage, sensor processing, RISC-V solutions for AI/ML from edge to cloud seems most blooming. As AI/ML continues to be the main driver of global semiconductor industry at least for the next several years, it creates further opportunity for RISC-V growth due to its extensibility to quickly support the latest innovations in AI/ML.

In this talk, we will first look at RISC-V’s successful stories in various applications and highlight AI/ML adoptions. We will examine the opportunities on fast-growing Edge AI applications, and the competitive advantages of RISC-V for AI/ML. We will then introduce Andes processor IP solutions for Intelligent Edge Application Processing, choices of SoC architecture and software support.

10:35 - 10:55

Empowering AI Innovation with Customized and Open-Source RISC-V Processors

Wei-Han, Lien｜Chief CPU Architect and Senior Fellow, Tenstorrent

Tenstorrent empowers AI innovation using versatile and open-source RISC-V processors. Our scalable AI accelerators, based on the Tensix core, utilize RISC-V for efficient control flow and data movement. Specialized vector and matrix engines enhance AI computation. The high-performance Ascalon RISC-V processor, with advanced features, supports heterogeneous computing, making it ideal for AI and server tasks. This open and modular approach enables high adaptability, performance, and efficiency across various AI applications, fostering innovation and meeting diverse computational needs.

10:55 - 11:10

Using the RISC-V ecosystem to build System-on-Chips (SoCs) for Artificial Intelligence (AI) applications

Mark Hayter｜Chief Strategy Officer & Co-Founder, Rivos Inc.

In this session, Mark Hayter shares the transformative benefits of using the RISC-V ecosystem to build System-on-Chips (SoCs) for Artificial Intelligence (AI) applications. As AI continues to drive advancements across various industries, the need for customizable, high-performance, power-efficient, and secure SoCs has never been greater. RISC-V, with its open and extensible instruction set architecture, offers unique advantages for meeting these demands.

The ability to combine open-source software with customized cores provides an immensely powerful SoC solution. This approach allows companies to develop products faster while maintaining a consistent software stack, providing a better user experience.

Mark demonstrates how combining open, commercial and custom RISC-V cores delivers an optimized high performance solution for AI workloads. He highlights the benefits of an open-standard architecture, collaboration on open-source software, and enabling diverse yet differentiated solutions within the industry.

11:10 - 11:30

Break & Exhibit Tour

11:30 - 12:10

RISC-V Trend and AI

Moderator:
Dr. Ryan Chen | Advisor, MediaTek Inc.

Panelist:

Lu Dai｜Board Chair, RISC-V International

Dr. Charlie Su｜President and CTO, Andes Technology

Wei-Han, Lien | Chief CPU Architect and Senior Fellow, Tenstorrent

Mark Hayter｜Chief Strategy Officer & Co-Founder, Rivos Inc.

12:10 - 13:30

Lunch/Exhibit Tour

13:30 - 13:50

Empowering RISC-V Software: Strengths, Challenges, and Opportunities in Open Source Collaboration

Barna Ibrahim｜Vice Chair, RISE Project

Join us for a session that highlights the strength and diversity of the RISC-V community, showcases RISE's (RISC-V Software Ecosystem) programs and investments, and emphasizes the importance of mobilizing open source developers and maintainers. Discover where RISC-V software excels and where challenges remain, and learn how to bring new projects to RISE’s attention. With RISE, RISC-V International, and the broader community collaborating closely, we aim to achieve parity with other architectures. Gain valuable insights into how RISE accelerates RISC-V software development, supports developer infrastructure and incentive programs, and how you can contribute to and benefit from the RISC-V software ecosystem.

Established in May 2023, the RISC-V Software Ecosystem (RISE) aims to accelerate software development in the RISC-V ecosystem by reducing barriers. RISE focuses on member information sharing, building developer infrastructure like build farms, and engaging the community through RFPs and a developer incentive program. RISE is dedicated to helping the RISC-V ecosystem flourish and achieve parity with other architectures.

13:50 - 14:05

The Golden Age of Computer Architecture with MIcrochip and RISC-V

Ted Speers｜Technical Fellow, Microchip Technology

Microchip's RISC-V journey began in 2015. It soon became evident that RISC-V was just one component of an expansive vision for the post-Moore world that David Patterson and John Hennessy articulated in their 2017 Turing Lecture entitled 'A New Golden Age for Computer Architecture'. This talk will give a progress report on the Golden Age, make projections on where it is headed, and illustrate how Microchip is poised bring the Golden Age to the Intelligent Edge.

14:05 - 14:20

RISC-V Adoption: Powered by AI

Travis Lanier｜Chief Product Officer, Ventana Micro Systems

This talk explores the potential of RISC-V for high-performance AI applications. We will discuss Ventana's approach to building scalable AI solutions, including:

High-Performance Cores: Leveraging server-grade RISC-V cores for demanding AI workloads.
Integration of Right-Sized Acceleration: Integration of vector/tensor units for AI tasks.
Streamlined Software Stack: Exploring how the open-source RISC-V ecosystem can facilitate efficient development.
Future-Proof Design: Examining the advantages of RISC-V and chiplets for building scalable and adaptable AI solutions.

14:20 - 14:40

Research Efforts of LLM SIG of RISC-V Taiwan Alliance

Prof. Tien-Fu, Chen｜Vice Chair / SIG Convener, RISC-V Taiwan Alliance

The rapid advancements in Large Language Models (LLMs) have revolutionized various domains, including IC design. Interesting topics may include two critical aspects: IC designs optimized for LLM and leveraging LLMs for the IC design process. RISC-V Taiwan Alliance already launched an LLM SIG, aiming at promoting and exchanging any LLM development and study or RISC-V. So far the activity is somehow not active, as most company members have limited resources and experience to share. However, we will share a few efforts in both aspects from an academic perspective. We hope that attendees can be attracted from gaining insights into the future of LLM technology and then are willing to join RVTA LLM advance hand in hand to push the boundaries of RISC-V technology.

14:40 - 15:00