[產業新聞] Rapid Silicon Licenses AndesCore™ D45 With DSP/SIMD Extensions And Andes Custom Extension™ Framework

發佈日期:2022/04/20

Andes Technology Corporation , a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology has taken a license for the AndesCore™ D45 with DSP/SIMD extensions as well as the Andes Custom Extension™ (ACE) framework. The superscalar 8-stage D45 RISC-V Core will be hardened and embedded into an FPGA to provide a full-speed CPU. The COPILOT tool of the ACE framework will allow designers to create their own CPU instructions that will be instantiated into the FPGA gates surrounding the hard-core CPU; at the same time, all required software development tools will be updated automatically by the COPILOT on designers’ desktop.

“We are delighted to offer our customers Andes high performance D45 CPU hard core with DSP/SIMD extensions in Rapid Silicon domain-specific, power, performance, and area (PPA) optimized FPGAs to target diverse applications in telecom, automotive, data processing and industrial vertical markets,” said Rapid Silicon’s Chairman & CEO, Dr. Naveed Sherwani. “To achieve a fast start to our ambitious goal of building the largest independent AI-enabled FPGA company, we needed silicon proven IP that could quickly and easily be added to our board-based FPGA. Furthermore, having an easy-to-use COPILOT development tool that enables Rapid Silicon to add our own custom instructions with little additional design time will shorten customers’ time to market considerably.”

“Andes Technology welcomes Rapid Silicon’s choice of our AndesCore™ D45 with DSP/SIMD extensions,” said Andes Chairman and CEO Frankwell Lin. “The D45 is popular with designers developing high performance signal processing applications.  In combination with COPILOT, the most user-friendly and production proven RISC-V custom extension development tool, designers can optimize their SoC to achieve the ideal combination of power, performance, area and application programmability. We wish Naveed great success with his new products.”